1. Field of the Invention
The present invention relates to an integrated structure active clamp for the protection of power devices, particularly, high-voltage MOSFETs and IGBTs, against overvoltages, and to a manufacturing process thereof.
2. Discussion of Related Art
The term "active clamp" refers to a circuit that is integrated on the same chip with a semiconductor power device to protect it from overvoltages.
The problems concerning the integration of active clamps in power devices have been discussed in the European Patent Application No. 93830200.7 filed on May 13, 1993 in the name of the same Applicant. In this document, an integrated structure protection circuit comprising a plurality of serially connected junction diodes between the gate and the drain of the power device is disclosed.
Parasitic components associated with this structure could generate incorrect functioning. For example, the first diode of the chain, connected to the gate of the power device, has a parasitic bipolar transistor associated with it; this bipolar transistor has a collector-emitter breakdown voltage (BV.sub.CES) equal to the drain-source breakdown voltage (BV.sub.DSS) of the power device. However, when the protection circuit operates the parasitic transistor is biased in the active region, the base current being equal to the current flowing through the protection circuit. This causes the collector-emitter voltage across the parasitic transistor, and thus the clamping voltage (Vclamp) of the protection circuit, to drop to a value (LV.sub.CEO) which is much lower than the BVCES, while the desired Vclamp should be just a little bit lower than the BV.sub.DSS.
Consequently, if the power device is a power MOSFET, it is necessary to increase the thickness of the epitaxial layer, i.e., its BV.sub.DSS, with the consequence of an undesired increase in the "on" resistance value (R.sub.DS(on)).
In the case of an Insulated Gate Bipolar Transistor (IGBT), due to the presence of a P+ substrate, the parasitic component is no longer a bipolar transistor, but an SCR, which can trigger a degenerative condition that could lead to the device destruction.
Different techniques for the integration of active clamps are known.
One of the known technique provides for the integration of a series of polysilicon diodes connected in parallel between the gate and the drain of the power device.
According to another technique, disclosed in JP-055202, dated Mar. 20, 1991, the active clamp features a polysilicon diode in series to a junction diode.
In U.S. Pat. No. 5,162,966 there is disclosed an N-channel MOSFET with gate shortcircuited to the drain and channel region connected to the source of the power MOSFET in series to a series of junction diodes.
In view of the state of the art just described, an object of the present invention is to accomplish an integrated structure active clamp in which the effects of parasitic components are minimized.